Add more registers to ISA, required for exploit.

2024-01-16 09:12:57 +01:00
parent ab724721c0
commit f244d69127
2 changed files with 34 additions and 17 deletions
--- a/tests/common.py
+++ b/tests/common.py
@@ -21,6 +21,12 @@ class Register(IntEnum):
    F = 5
    G = 6
    H = 7
+    I = 8
+    J = 9
+    K = 10
+    L = 11
+    M = 12
+    N = 13


 INSTR_LEN = 8